1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a method for fabricating the same, a bias is applied to a body in a silicon on insulator (SOI) MOSFET, effectively reducing or eliminating a floating body effect otherwise experienced by the semiconductor device.
2. Discussion of the Related Art
A conventional semiconductor device will be described hereinafter with reference to the accompanying drawings.
FIG. 1 is a sectional view illustrating a structure of a conventional SOI MOSFET.
As shown in FIG. 1, in an SOI MOSFET, an SOI substrate is formed by a SIMOX(Separation by IMplantation of OXygen) method, a BESOI(Bonded and Etchback SOI) method, or a smart-cut method.
The conventional MOSFET includes a buried oxide film 2 formed on a semiconductor substrate 1 at a thickness of 1000xcx9c4000 xc3x85, an isolation layer 3 formed by LOCOS or STI process, surface silicon layers formed on the buried oxide film 2 at a thickness of 500xcx9c2000 xc3x85 to form source/drain regions 4 and 6 and a channel region 5, a gate insulating film 7 formed on the channel region 5, a gate electrode 8 formed on the gate insulating film 7, an interleave insulating layer 9 formed on the gate electrode 8 and transistors of the source/drain regions 4 and 6 to selectively form a contact hole, and a metal electrode layer 10 connected to the source/drain regions 4 and 6 and the gate electrode 8 through the contact hole of the interleave insulating layer 9.
A thermal oxide film having a thickness of 50xcx9c100 xc3x85, which is grown by thermal oxidation process, is mainly used as the gate insulating film 7.
An impurity ion is implanted into the channel region 5 to adjust a threshold voltage.
If the MOSFET is an NMOS transistor, B or BF2 is used as the impurity ion. Alternatively, if the MOSFET is a PMOS transistor, P or As is used as the impurity ion.
A doped polysilicon is mainly used as the gate electrode 8. If the MOSFET includes both NMOS and PMOS transistors, n+ type doped polysilicon may be used as the gate electrode 8. An n+ type doped polysilicon may also be used as the gate electrode 8 if the MOSFET is an NMOS transistor, but a p+ type doped polysilicon may be used as the gate electrode 8 if the MOSFET is a PMOS transistor.
After the gate electrode 8 is formed, the impurity ion is implanted to form the source/drain regions 4 and 6. For NMOS transistors, As is implanted at a dose of 2xcx9c5E15cmxe2x88x922. For PMOS transistors, B or BF2 is implanted at a dose of 1xcx9c3E15cmxe2x88x922.
At this time, a lightly doped drain (LDD) region may be formed to prevent the deterioration of device characteristic due to hot carriers.
The SOI device serves as a conventional bulk device. The channel region of the NMOS and PMOS transistors in these conventional MOSFET devices remains floating. Therefore, in the NMOS transistor, a floating body effect may be experienced since holes may accumulate in a body based on alpha particles or in the course of operating the device.
Due to this floating body effect, the conventional semiconductor device is susceptible to several problems. For instance, the breakdown voltage may be reduced by the floating body effect, and distortion may occur in Id-Vd curve, thereby deteriorating characteristic of the device. Further, an abnormal slope of subthreshold may occur and the operation of the device may become unstable due to transient effect in the course of AC operation.
The present invention is directed to a semiconductor device and a method for fabricating the same that substantially obviate one or more of the above and other problems experienced by conventional devices due to limitations and disadvantages of the related art.
An object of the present invention is to provide a semiconductor device and a method for fabricating the same in which a bias is applied to a body in an SOI MOSFET, thereby reducing or eliminating a floating body effect.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a semiconductor device according to the present invention includes first and second impurity ion implanting layers of a conductivity type formed in a semiconductor substrate having a buried oxide film and surface silicon layers thereon, first and second transistors of a conductivity type respectively formed on the first and second impurity ion implanting layers, having source/drain regions and a gate, trenches formed between the first and second transistors, single crystal silicon layers connected to any one of the source/drain regions of the respective transistors and the first and second impurity ion implanting layers at sides of the trenches, and carrier exhausting electrodes connected to the first and second impurity ion implanting layers at one sides of the respective transistors, for exhausting carrier generated by ionization impact in the respective transistors.
In another aspect, a method for fabricating a semiconductor device according to the present invention includes the steps of sequentially forming a pad oxide film and a nitride film on a semiconductor substrate having a buried oxide film and surface silicon layers thereon, selectively etching the pad oxide film and the nitride film to form trenches, forming undoped polysilicon sidewalls at sides of the trenches, thermally oxidizing outer sides of the undoped polysilicon sidewalls to form a first dielectric layer, recrystallizing inner sides of the undoped polysilicon sidewalls using the silicon layers and a body of the semiconductor substrate as seeds to form single crystal silicon layers, depositing an oxide film on an entire surface including the trenches and planarizing the oxide film to form a second dielectric layer, selectively removing the nitride film and the pad oxide film, forming a first photoresist and patterning the first photoresist to remain on a portion where a PMOS transistor will be formed, implanting an impurity ion into a channel region of the surface silicon layers and single crystal silicon layer at one sides of the trenches, and the body of the semiconductor substrate using the first photoresist as a mask, forming a gate oxide film and a gate electrode on the channel region into which the impurity ion is implanted, selectively implanting the impurity ion into the gate oxide film and the gate electrode to form source/drain regions, and forming carrier exhausting electrodes on the surface silicon layers at the other sides of the trenches.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.